11.12 update

cores/logic_gate_and.v

@@ -7,8 +7,19 @@ module logic_gate_and #
     parameter integer OUT = 0
 )
 (
-    input wire din,
-    output wire led
+    input wire [7:0] din,
+    output wire [7:0] led
 );
-    assign led[OUT] = din[IN1] & din[IN2];
+    wire [7:0] tmp;
+    
+    assign tmp[0] = din[IN1] & din[IN2];
+    assign tmp[1] = din[IN1] & din[IN2];
+    assign tmp[2] = din[IN1] & din[IN2];
+    assign tmp[3] = din[IN1] & din[IN2];
+    assign tmp[4] = din[IN1] & din[IN2];
+    assign tmp[5] = din[IN1] & din[IN2];
+    assign tmp[6] = din[IN1] & din[IN2];
+    assign tmp[7] = din[IN1] & din[IN2];
+
+    assign led = tmp;
 endmodule