axis_tagger.v 986 B

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  1. `timescale 1 ns / 1 ps
  2. module axis_tagger #
  3. (
  4. parameter integer AXIS_TDATA_WIDTH = 256
  5. )
  6. (
  7. // System signals
  8. input wire aclk,
  9. input wire tag_data,
  10. // Slave side
  11. output wire s_axis_tready,
  12. input wire [AXIS_TDATA_WIDTH-1:0] s_axis_tdata,
  13. input wire s_axis_tvalid,
  14. // Master side
  15. input wire m_axis_tready,
  16. output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
  17. output wire m_axis_tvalid
  18. );
  19. reg int_data_reg, int_flag_reg;
  20. always @(posedge aclk)
  21. begin
  22. int_data_reg <= tag_data;
  23. if(tag_data & ~int_data_reg)
  24. begin
  25. int_flag_reg <= 1'b1;
  26. end
  27. else if(s_axis_tvalid)
  28. begin
  29. int_flag_reg <= 1'b0;
  30. end
  31. end
  32. assign s_axis_tready = m_axis_tready;
  33. assign m_axis_tdata = {s_axis_tdata[255:209], int_flag_reg, s_axis_tdata[207:0]};
  34. assign m_axis_tvalid = s_axis_tvalid;
  35. endmodule