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Debug Build logic_tesr

Vyacheslav Vinokurov 1 week ago
parent
commit
6999ae2cc2
3 changed files with 372 additions and 9 deletions
  1. 355 0
      .gitignore
  2. 12 5
      cores/logic_gate_and.v
  3. 5 4
      projects/logic_test/block_design.tcl

+ 355 - 0
.gitignore

@@ -0,0 +1,355 @@
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+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_7s_mmcm.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_7s_pll.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_us_mmcm.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_us_pll.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_us_plus_mmcm.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/a9be/mmcm_pll_drp_func_us_plus_pll.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_0.vh
+tmp/logic_test.gen/sources_1/bd/system/ipshared/ec67/hdl/axi_infrastructure_v1_1_vl_rfs.v
+tmp/logic_test.gen/sources_1/bd/system/ipshared/f16f/hdl/axi_vip_v1_1_vl_rfs.sv
+tmp/logic_test.gen/sources_1/bd/system/sim/system.protoinst
+tmp/logic_test.gen/sources_1/bd/system/sim/system.v
+tmp/logic_test.gen/sources_1/bd/system/synth/system.hwdef
+tmp/logic_test.gen/sources_1/bd/system/synth/system.v
+tmp/logic_test.hw/logic_test.lpr
+tmp/logic_test.srcs/sources_1/bd/system/system.bd
+tmp/logic_test.srcs/sources_1/bd/system/system.bda
+tmp/logic_test.srcs/sources_1/bd/system/ip/system_and_1_0/system_and_1_0.xci
+tmp/logic_test.srcs/sources_1/bd/system/ip/system_pll_0_0/system_pll_0_0.xci
+tmp/logic_test.srcs/sources_1/bd/system/ip/system_ps_0_0/system_ps_0_0.xci

+ 12 - 5
cores/logic_gate_and.v

@@ -1,7 +1,14 @@
-module logic_gate_and(
-    input din1
-    input din2
-    output led
+`timescale 1 ns / 1 ps
+
+module logic_gate_and #
+(
+    parameter integer IN1 = 0,
+    parameter integer IN2 = 1,
+    parameter integer OUT = 0
 )
-    assign led = din1 & din2
+(
+    input wire din,
+    output wire led
+);
+    assign led[OUT] = din[IN1] & din[IN2];
 endmodule

+ 5 - 4
projects/logic_test/block_design.tcl

@@ -25,8 +25,9 @@ apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
   Slave Disable
 } [get_bd_cells ps_0]
 
-cell v-vinokurov:user:logic_gate_and and_1 { } {
-    din1 exp_p_tri_io[0]
-    din2 exp_p_tri_io[1]
-    led exp_n_tri_io[0]
+cell v-vinokurov:user:logic_gate_and and_1 {
+    IN1 0 IN2 1 OUT 0
+ } {
+    din exp_p_tri_io
+    led exp_n_tri_io
 }