update logic_gate 2

cores/logic_gate_and.v

@@ -1,4 +1,4 @@
-module logic_and_gate(
+module logic_gate_and(
     input din1
     input din2
     output led

projects/logic_test/block_design.tcl

@@ -25,7 +25,7 @@ apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
   Slave Disable
 } [get_bd_cells ps_0]
 
-cell v-vinokurov:user:logic_and_gate and_1 { } {
+cell v-vinokurov:user:logic_gate_and and_1 { } {
     din1 exp_p_tri_io[0]
     din2 exp_p_tri_io[1]
     led exp_n_tri_io[0]