update logic_gate

cores/logic_gate_and.v

@@ -1,7 +1,7 @@
 module logic_and_gate(
-    input exp_p_tri_io[0]
-    input exp_p_tri_io[1]
-    output exp_n_tri_io[0]
+    input din1
+    input din2
+    output led
 )
-    assign exp_n_tri_io[0] = exp_p_tri_io[0] & exp_p_tri_io[0]
+    assign led = din1 & din2
 endmodule

projects/logic_test/block_design.tcl

@@ -0,0 +1,32 @@
+cell xilinx.com:ip:clk_wiz pll_0 {
+  PRIMITIVE PLL
+  PRIM_IN_FREQ.VALUE_SRC USER
+  PRIM_IN_FREQ 125.0
+  PRIM_SOURCE Differential_clock_capable_pin
+  CLKOUT1_USED true
+  CLKOUT1_REQUESTED_OUT_FREQ 125.0
+  USE_RESET false
+} {
+  clk_in1_p adc_clk_p_i
+  clk_in1_n adc_clk_n_i
+}
+
+# Create processing_system7
+cell xilinx.com:ip:processing_system7 ps_0 {
+  PCW_IMPORT_BOARD_PRESET cfg/red_pitaya.xml
+} {
+  M_AXI_GP0_ACLK pll_0/clk_out1
+}
+
+# Create all required interconnections
+apply_bd_automation -rule xilinx.com:bd_rule:processing_system7 -config {
+  make_external {FIXED_IO, DDR}
+  Master Disable
+  Slave Disable
+} [get_bd_cells ps_0]
+
+cell v-vinokurov:user:logic_and_gate and_1 { } {
+    din1 exp_p_tri_io[0]
+    din2 exp_p_tri_io[1]
+    led exp_n_tri_io[0]
+}