LFMRI_firmware/cores/logic_gate_and.v

`timescale 1 ns / 1 ps

module logic_gate_and #
(
    parameter integer IN1 = 0,
    parameter integer IN2 = 1,
    parameter integer OUT = 0
)
(
    input wire din,
    output wire led
);
    assign led[OUT] = din[IN1] & din[IN2];
endmodule