pulse_generator.v 1.3 KB

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  1. `timescale 1 ns / 1 ps
  2. module pulse_generator #
  3. (
  4. parameter CONTINUOUS = "FALSE"
  5. )
  6. (
  7. input wire aclk,
  8. input wire aresetn,
  9. input wire [95:0] cfg,
  10. output wire dout
  11. );
  12. reg int_dout_reg, int_dout_next;
  13. reg [31:0] int_cntr_reg, int_cntr_next;
  14. always @(posedge aclk)
  15. begin
  16. if(~aresetn)
  17. begin
  18. int_dout_reg <= 1'b0;
  19. int_cntr_reg <= 32'd0;
  20. end
  21. else
  22. begin
  23. int_dout_reg <= int_dout_next;
  24. int_cntr_reg <= int_cntr_next;
  25. end
  26. end
  27. always @*
  28. begin
  29. int_dout_next = int_dout_reg;
  30. if(int_cntr_reg == cfg[31:0])
  31. begin
  32. int_dout_next = 1'b1;
  33. end
  34. if(int_cntr_reg == cfg[63:32])
  35. begin
  36. int_dout_next = 1'b0;
  37. end
  38. end
  39. generate
  40. if(CONTINUOUS == "TRUE")
  41. begin : CONTINUE
  42. always @*
  43. begin
  44. int_cntr_next = int_cntr_reg;
  45. if(int_cntr_reg < cfg[95:64])
  46. begin
  47. int_cntr_next = int_cntr_reg + 1'b1;
  48. end
  49. else
  50. begin
  51. int_cntr_next = 32'd0;
  52. end
  53. end
  54. end
  55. else
  56. begin : STOP
  57. always @*
  58. begin
  59. int_cntr_next = int_cntr_reg;
  60. if(int_cntr_reg < cfg[95:64])
  61. begin
  62. int_cntr_next = int_cntr_reg + 1'b1;
  63. end
  64. end
  65. end
  66. endgenerate
  67. assign dout = int_dout_reg;
  68. endmodule