axis_selector.v 1.4 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647
  1. `timescale 1 ns / 1 ps
  2. module axis_selector #
  3. (
  4. parameter integer AXIS_TDATA_WIDTH = 32
  5. )
  6. (
  7. // System signals
  8. input wire aclk,
  9. input wire aresetn,
  10. input wire cfg_data,
  11. // Slave side
  12. input wire [AXIS_TDATA_WIDTH-1:0] s00_axis_tdata,
  13. input wire s00_axis_tvalid,
  14. output wire s00_axis_tready,
  15. input wire [AXIS_TDATA_WIDTH-1:0] s01_axis_tdata,
  16. input wire s01_axis_tvalid,
  17. output wire s01_axis_tready,
  18. // Master side
  19. output wire [AXIS_TDATA_WIDTH-1:0] m_axis_tdata,
  20. output wire m_axis_tvalid,
  21. input wire m_axis_tready
  22. );
  23. wire [AXIS_TDATA_WIDTH-1:0] int_data_wire;
  24. wire int_valid_wire, int_ready_wire;
  25. assign int_data_wire = cfg_data ? s01_axis_tdata : s00_axis_tdata;
  26. assign int_valid_wire = cfg_data ? s01_axis_tvalid : s00_axis_tvalid;
  27. assign s00_axis_tready = ~cfg_data & int_ready_wire;
  28. assign s01_axis_tready = cfg_data & int_ready_wire;
  29. inout_buffer #(
  30. .DATA_WIDTH(AXIS_TDATA_WIDTH)
  31. ) buf_0 (
  32. .aclk(aclk), .aresetn(aresetn),
  33. .in_data(int_data_wire), .in_valid(int_valid_wire), .in_ready(int_ready_wire),
  34. .out_data(m_axis_tdata), .out_valid(m_axis_tvalid), .out_ready(m_axis_tready)
  35. );
  36. endmodule