`timescale 1 ns / 1 ps

module logic_gate_and #
(
    parameter integer IN1 = 0,
    parameter integer IN2 = 1,
    parameter integer OUT = 0
)
(
    input wire [7:0] din,
    output wire [7:0] led
);
    wire [7:0] tmp;
    
    assign tmp[0] = din[IN1] & din[IN2];
    assign tmp[1] = din[IN1] & din[IN2];
    assign tmp[2] = din[IN1] & din[IN2];
    assign tmp[3] = din[IN1] & din[IN2];
    assign tmp[4] = din[IN1] & din[IN2];
    assign tmp[5] = din[IN1] & din[IN2];
    assign tmp[6] = din[IN1] & din[IN2];
    assign tmp[7] = din[IN1] & din[IN2];

    assign led = tmp;
endmodule